Electronic systems typically store data during operation in a memory device. In recent years, the dynamic random access memory (DRAM) has become a popular data storage device for such systems. Basically, a DRAM is an integrated circuit that stores data in binary form (e.g., "1" or "0") in a large number of cells. Each memory cell includes a capacitor that stores the data in the cell and a transistor that controls access to the data. The capacitor includes two conductive plates. One plate of each capacitor is typically coupled to a common node with a plate of each of the other capacitors. This plate is referred to as the "cell plate. " The charge stored across the capacitor is representative of a data bit and can be either a high voltage or a low voltage.
Typically, the cells of a DRAM are arranged in an array so that individual cells can be addressed and accessed. The array can be thought of as rows and columns of cells. Each row includes a word line that interconnects cells on the row with a common control signal. Similarly, each column includes a bit line that is coupled to at most one cell in each row. Thus, the word and bit lines can be controlled so as to individually access each cell of the array.
To read data out of a cell, the capacitor of a cell is accessed by selecting the word line associated with the cell. A complimentary bit line that is paired with the bit line for the selected cell is equilibrated with the voltage on the bit line for the selected cell. When the word line is activated for the selected cell, the capacitor of the selected cell discharges the stored voltage onto the bit line, thus changing the voltage on the bit line. A sense amplifier detects and amplifies the difference in voltage on the pair of bit lines. An input/output device for the array, typically an n-channel transistor, passes the voltage on the bit line for the selected cell to an input/output line for communication to, for example, a processor of a computer or other electronic system associated with the DRAM. In a write operation, data is passed from the input/output lines to the bit lines by the input/output device of the array for storage on the capacitor in the selected cell.
Recently, researchers have proposed a new architecture for sensing the voltage stored in the cells of a memory device that is aimed at increasing the voltage differential of the bit line pair. According to this new architecture, the cell plate is divided into a number of lines that are each paired with a bit line. The bit line/plate line pairs are coupled to sense amplifiers which read and write data to and from the cells. One problem with this architecture is the difficulty in equilibrating the bit line/plate line pairs when reading data out of a cell without destroying data stored in other cells on the same plate line since the voltage on the plate line is allowed to fluctuate.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device that implements a dynamic cell plate sensing scheme with ac equilibration wherein data is not corrupted during a read operation.